1. Field of the Invention
The present invention relates in general to a process for fabricating semiconductor MOS transistor devices. In particular, the present invention relates to a process for fabricating MOS transistor devices having a full-overlap lightly-doped drain structural configuration. More particularly, the present invention relates to a process for fabricating MOS transistor devices having a full-overlap lightly-doped drain structure that are suitable for semiconductor circuit integration and provide improved operational characteristics.
2. Technical Background
As the semiconductor technology of integrated circuit fabrication advances, the components constituting the electronic circuitry in the IC are becoming ever smaller in their physical dimensions. In semiconductor fabrication processes that employ resolutions in the submicron range, thermal electrons trapped in gates of MOS transistors of an IC device have become a significant factor affecting the operational reliability of the device itself. A brief description of a conventional MOS transistor with a lightly-doped drain, as well as its process of fabrication, is examined below to assist in the understanding of the disclosure of the present invention.
A conventional MOS transistor device having lightly-doped drain (hereafter referred to as LDD MOS transistor), together with the process employed in its fabrication is depicted in FIGS. 1a-1d, which schematically show in cross-sectional views a conventional LDD MOS transistor in selected process stages of its fabrication.
Referring to FIG. 1a, P-type semiconductor substrate 1 has formed at the designated locations two field oxide layers 1a. Gate oxide layer 100 and polysilicon layer 102 are then formed over the surface of substrate 1 providing gate 10 for the MOS transistor to be fabricated.
Then, referring to FIG. 1b, gate 10 and field oxide layers 1a are utilized as the shielding mask for implanting N-type impurities, such as arsenic, into the predetermined depth of P-type substrate 1, thereby forming lightly-doped regions 12.
Then, as is seen in FIG. 1c, sidewall spacers 120 are formed over the sidewalls of gate 10. This is done by, for example, first depositing a layer of nitride, and then performing a plasma etching procedure to remove all other portions of the deposited nitride layer, thereby forming sidewall spacers 120.
Next, referring to FIG. 1d, field oxide layers 1a, sidewall spacers 120, as well as gate 10 are utilized as the shielding mask for implanting the same N-type impurities to form the heavily-doped regions, which in this descriptive prior art example are N-type doped regions 14 as shown in the drawing. A portion of each of lightly-doped regions 12 remains unaffected by the impurity implantation. This allows the formation of drain and source regions for the MOS transistor each having a lightly-doped portion.
However, because MOS transistors are getting ever smaller in their physical dimensions, the transistor channel region located between the drain and source regions is also getting small in dimension as well. This enlarges the relative ratio of the area for the lightly-doped region to that of the transistor channel region. Since the electrical impedance value in the lightly-doped region is larger than that of the heavily-doped regions, the overall operational characteristics of the MOS transistor therefore deteriorate. The phenomena of punch-through in the transistor channel region is more likely to happen, thereby disadvantageously disabling the operation of the MOS transistor.